AM5 Pinout

  Socket_AM5_pinmap.pdf (875,5 КиБ, 7 hits)

Pin Description

Signal Description
MA/MB_ALERT_L DRAM Channel A/B Alert (CRC error and Command/Address parity error)
MA/MB_RESET_L DRAM Channel A/B DIMM Reset
MAA/MAB/MBA/MBB_CA[13:0] DRAM Channel A/B Subchannel A/B Command/Address Bus
MAA/MAB/MBA/MBB_CHECK[3:0] DRAM Channel A/B Subchannel A/B ECC Check Byte
MAA/MAB/MBA/MBB_DATA[31:0] DRAM Channel A/B Subchannel A/B Data Bus
MAA/MAB/MBA/MBB_DM[3:0] DRAM Channel A/B Subchannel A/B Data Mask
MAA/MAB/MBA/MBB_DQS_H/L[4:0] DRAM Channel A/B Subchannel A/B Data Strobe Differential Pair
MAA0/MAB0/MBA0/MBB0_CLK_H/L[1:0]
MAA1/MAB1/MBA1/MBB1_CLK_H/L[1:0]
DRAM Channel A/B DIMM 0/1 Subchannel A/B Differential Clock
MAA0/MAB0/MBA0/MBB0_CS_L[1:0]
MAA1/MAB1/MBA1/MBB1_CS_L[1:0]
DRAM Channel A/B DIMM 0/1 Subchannel A/B Chip Select
PCIE_RXP/RXN[27:0] PCIe Receive Data Differential Pairs
PCIE_TXP/TXN[27:0] PCIe Transmit Data Differential Pairs
PCIE_RST0_L Reset for PCIe devices or SPI TPM
DP0-DP3_TXP/TXN[3:0] DisplayPort 0-3 Main Link Differential Transmitter Lane 0-3 or DVI/HDMI Channel 2, 1, 0, Clock
DP0-DP3_AUXP/AUXN DisplayPort 0-3 Auxiliary Channel or DVI/HDMI DDC Clock, Data
DP0-DP3_HPD DisplayPort 0-3 Hot Plug Detect Input
DP0_BLON Display Panel Backlight Enable
DP0_DIGON Display Panel Power Enable
DP0_VARY_BL Display Backlight Brightness Control
DP_STEREOSYNC StereoSync output for shutter glasses
USBC(0-2)_RX1P/RX1N USB Port 0-2 USB-C Receive Differential Pairs or DisplayPort Transmitter Lane 3
USBC(0-2)_TX1P/TX1N USB Port 0-2 USB-C Transmit Differential Pairs or DisplayPort Transmitter Lane 2
USBC(0-2)_RX2P/RX2N USB Port 0-2 USB-C Receive Differential Pairs or DisplayPort Transmitter Lane 0
USBC(0-2)_TX2P/TX2N USB Port 0-2 USB-C Transmit Differential Pairs or DisplayPort Transmitter Lane 1
USB(0-3)_RXP/RXN USB Port 0-3 USB3 Super Speed Receive Differential Pairs
USB(0-3)_TXP/TXN USB Port 0-3 USB3 Super Speed Transmit Differential Pairs
USBC(0-2)_DP/DN
USB(0-4)_DP/DN
USB Port 0-4 USB2 I/O Differential Pairs
USBC(0-1)_SBRX/SBTX USB Port 0-1 USB4 Sideband Interface (alt. func. of DP1_AUX, DP2_AUX)
USBC_I2C_SCL I2C Clock for USB-C PD Control
USBC_I2C_SDA I2C Data for USB-C PD Control
USBC_PD_INT USB-C Power Delivery Interrupt
USB_BIOS_UPDATE USB BIOS Update Function (momentary switch)
USB_OC(0-3)_L USB Over Current signal from USB connector
AZ_BITCLK Azalia HD Audio Interface Bit Clock
AZ_RST_L HDA Reset
AZ_SDIN(0-2) HDA Serial Data Input from Codec 0-2
AZ_SDOUT HDA Serial Data Output to Codec
AZ_SYNC HDA Sync signal to Codec
DMIC_CLK Digital Microphone Clock Output
DMIC_DATA0 DMIC Data Input (2 ch PDM)
DMIC_DATA1 DMIC Data (alt. func. of AZ_BITCLK or AZ_SDIN1)
DMIC_DATA2 DMIC Data (AZ_SYNC or AZ_SDIN2)
SW0_MCLK SoundWire Interface 0 Clock (AZ_SDIN1)
SW0_MDATA(0-3) SW0 Data (AZ_SDIN2, AZ_RST_L, AZ_SDOUT, AZ_SDIN0)
SW1_MCLK SoundWire Interface 1 Clock (AZ_BITCLK)
SW1_MDATA0 SW1 Data (AZ_SYNC)
SPKR PC speaker/beeper PWM output
SPI/SPI1_CLK SPI Clock Output
SPI/SPI1_DAT[0] SPI Data 0 for multi-I/O device or Data Out
SPI/SPI1_DAT[1] SPI Data 1 for multi-I/O device or Data In
SPI/SPI1_DAT[3:2] SPI Data 2, 3 for multi-I/O device
SPI/SPI1_CS(1-2)_L Chip Select for SPI ROM
SPI_TPM_CS_L Chip Select for SPI TPM
SPI_ROM_REQ SPI ROM Request
SPI_ROM_GNT SPI ROM Grant
ESPI_CLK ESPI Clock Output
ESPI_DAT[3:0] ESPI Data[0], Data[1:0], Data[3:0] Input/Output
ESPI_CS_L ESPI Chip Select
ESPI_ALERT_L ESPI Alert Input
ESPI_RESET_L ESPI Reset Input (ESPI_RESET_L/KBRST_L)
I3C(0-3)_SCL I3C Bus 0-3 Clock
I3C(0-3)_SDA I3C Bus 0-3 Data
I2C(0-3)_SCL I2C Bus 0-3 Clock (alt. func. of I3C0-I3C3)
I2C(0-3)_SDA I2C Bus 0-3 Data
SMBUS(0-1)_SCL SMBus 0-1 Clock (I3C2, I3C3)
SMBUS(0-1)_SDA SMBus Data
AGPIO* Advanced GPIO pin for interrupt, wake, or I/O
EGPIO* Enhanced GPIO for I/O only
GENINT(1-2)_L Generic Interrupt Request
GPP_CLK(0-5)P/N 100 MHz Differential PCIe Reference Clock Outputs
CLK_REQ(0-5)_L PCIe Clock Request
X32K_X1/X2 32768 Hz Real Time Clock XTAL
X48M_X1/X2 48 MHz clock XTAL for the integrated clock generator
X48M_OSC 48 MHz clock output for devices requiring a single-ended OSC input
RTCCLK 32768 Hz Real Time Clock output for a device requiring an RTC clock
BLINK Blink LED S-state Indicator
KBRST_L Keyboard Controller Reset Input (warm reset)
PWR_GOOD Power Good Input; Asserted when all voltages are within specification
PWR_BTN_L Power Button Input; Requests sleep state or causes wake event
PWROK
RESET_L Reset signal
RSMRST_L Resume Reset; Asserted on power up, deasserted when S5 power supplies are within specification
S0A3_GPIO
SLP_S3/S5_L S3/S5 Sleep State Power Plane Control Signals for voltage regulator
SYS_RESET_L System Reset Input (reset button)
WAKE(0-3)_L PCIe WAKE_L signal, wake system out of sleep state
WAKE(4-5)_L PCIe WAKE_L signal (alt. func. of USB_OC1, USB_OC2)
ALERT_L SB-TSI Interrupt
FANIN0 Fan 0 tachometer input
FANOUT0 Fan 0 PWM output
PROCHOT_L Asserted to force the processor into HTC-active state
SIC Sideband Interface (SB-TSI) Clock
SID Sideband Interface Data
THERMTRIP_L Temperature Trip Output
DBREQ_L Debug Request input to JTAG controller
TCK JTAG Clock
TDI JTAG Data Input
TDO JTAG Data Output
TMS JTAG Mode Select
TRST_L JTAG Reset
TEST* Test/Debug signals
CCD_ANALOG_TEST
PCC_L
SVC Serial VID Clock; (SVI3) interface to VDDCR/VDDCR_SOC regulator
SVD Serial VID Data
SVT Serial VID Telemetry
VDDBT_RTC_G Integrated Real Time Clock battery power supply
VDDCR Core power supply
VDDCR_SENSE Differential (with VSS_SENSE_A) feedback for VDDCR regulator
VDDCR_SOC Power supply for integrated Northbridge
VDDCR_SOC_SENSE Differential (with VSS_SENSE_A) feedback for VDDCR_SOC regulator
VDDIO_AUDIO
VDDIO_MEM_S3
VDDIO_MEM_S3_SENSE
VDD_18 1.8 V supply voltage for analog circuits
VDD_18_S5 Always on 1.8 V supply voltage for analog circuits
VDD_33 3.3 V supply voltage
VDD_33_S5 Always on 3.3 V supply voltage
VDD_MISC Power supply for DisplayPort and PCIe PHY logic
VDD_MISC_SENSE Differential feedback for VDD_MISC regulator
VDD_MISC_S5 Power supply for USB physical layer
VDD_MISC_S5_SENSE Differential (with VSS_SENSE_B) feedback for VDD_MISC_S5 regulator
VSS Ground
VSS_SENSE_A VSS Sense pin for VDDCR/VDDCR_SOC regulator
VSS_SENSE_B VSS Sense pin for VDD_MISC regulator
AM5R1 Processor family revision identifier; NC = Not connected, VSS = connected to VSS on the package

Processor AM5R1
Type-1/2/3 NC
AUX(0-5)_RST_L
OSCIN
RSVD Reserved
SMU_ZVDD_ODPR(0-2)
TMU_CLK_OUT

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